In general every analog block within an integrated circuit needs a current bias to allow for proper operation. A main current bias distribution within a chip can be a current source that is distributed with in an integrated circuit chip by means of a few current mirror circuits. The bias current circuit causes additional power consumption.
Because the bias current circuit is additional power consumption for the chip, the actual used value is small, especially in very low power design, which can be down to a few tenths of a nano-amp. Such a small current is prone to being disturbed by other circuitry on the chip and sometimes by the biased block itself. In order to filter such a noise disturbance, a simple low pass filter usually created by a normal capacitor or MOS capacitor is added.
US 2013/0033104 A1 (Gunther et al.) is directed to a system that includes a start-up circuit that compares a feedback voltage to an output voltage. US 2011/0274290 A1 (Holzmann et al.) is directed to a driver device with a bias circuit that includes a buffer for rapidly charging an external capacitance. US 2005/0134344 A1 (Ro) is directed to a method and a system to provide a fast start-up circuit for a pre-scaler device. US 2004/0113706 A1 (Yen et al.) is directed to a fast start-up oscillator, which provide a fast stabilized voltage source. U.S. Pat. No. 8,283,974 B2 (Chu et al.) is directed to a fast start-up low voltage bandgap reference voltage generator.
In FIG. 1 is shown a bias circuit of prior art, wherein a main current bias, Ibias, is distributed by means of current mirrors like N1 and Nx. Since the bias current is additional power consumption, the actual amount used is reasonably small, especially in very low power design that can be down to few tenths of nano-amps. These small current amounts are prone to be disturbed by other circuitry on the chip, which can be sometimes disturbed by the biased block itself. A simple low pass filter, usually created by a normal capacitor or MOS capacitor is added to filter noise and disturbance from other circuitry. This capacitor might be also created by the input gate capacitance of all the mirror transistors which are connected to the nbias node so it disappears from the schematic, but it is still present. It is depicted in FIG. 1 as C1. This low pass filter filters the nbias node voltage and makes the currents Ibias_2 and. Ibias_x less noisy.
Using capacitance C1 to filter noise has a drawback, which is long start-up time of the circuit. When the block is disabled, the disable switch S2 is ON and enable switch S1 is OFF. This means the nbias voltage is 0V, and voltage at nswitch is equal to Vdd. When the current bias is enabled, the disable switch S2 is turned OFF and enable switch S1 is turned ON. Bias current starts flowing from drain of P2, which starts the charging of C1. At that moment no current is flowing through Ibias_2 through Ibias_x branches. The voltage in nbias is increasing as C1 is being charged and finally at the moment when the nbias reaches threshold voltage of the transistor Nx, the current in the branches ‘Ibias_x’ starts flowing. It takes even a longer time until the current in the Ibias_x branch is fully settled.
FIG. 2 shows waveforms at key locations in the circuit of FIG. 1. As switch S1 is closed, switch S2 is opened, causing voltage at node nswitch to fall to ground before recovering to nbias that is between Vdd and 0V. The current Ibias 2 is somewhat delayed beyond the start of nbias until the gate of the N2 transistor is brought up to a threshold voltage.